Job Description (Posting). The ideal candidate will apply their experience and sharpen their expertise in a hard-core product development environment. The Senior Hardware Engineer will be responsible for implementing functionalities such as DSP algorithms and communication protocols, high-speed interface protocols, and networking protocols in Field Programmable Gate Arrays (FPGAs). The ideal candidate should also have some level of experience with digital board design and understanding of high-speed digital design principles.Responsibilities Rapidly develop concept to prototype, including digital, analog, and FPGA components. Develop all aspects of FPGA implementation, with emphasis on design partitioning, RTL synthesis and simulation, place and route, timing closure, IP integration, and system level debugging. Work with cross-functional teams to define engineering requirements based on system-level requirements and tradeoffs. Create formal engineering documentation including SRS, SDD, ICD, and others. Bring-up and bench testing of prototype electronics. Work with manufacturing team to bring up production.Minimum qualifications BS degree in Electrical Engineering. Eight (8) years of experience with FPGA development in VHDL or Verilog as well as board-level design including FPGA selection, digital design, basic analog circuitry (filter/gain stages) including ADCs, DACs, switching voltage regulators, and platform bring-up. Hands on experience and a solid understanding in some or all of the following: common bus interfaces and IO's such as Gigabit Ethernet, JESD204, PCIe, USB, IC2, and JTAG. Hands on experience and a solid understanding in some or all of the following FPGA design tools: Altera (Intel) Quartus, Xilinx Vivado, Aldec Active-HDL or Riviera-PRO, Modelsim, and version control such as Subversion or git. Experience in PCB schematic & layout software (e.g. Orcad). Ability to direct PCB designers. Experience with architecture and design of communications systems. Basic proficiency with C for embedded systems and one higher level language (Python, etc). Experience with using lab instruments; oscilloscope, logic analyzer, spectrum analyzer, signal generator.Preferred qualifications MS or PhD in Electrical Engineering or Communications Engineering. Experience modeling DSP algorithms (FFT, filters) and communication waveforms in MATLAB / Python / etc. In-depth understanding of different FPGA architectures especially as it relates to communications design. Demonstrated leadership and mentoring skills. (1.) Prepare and own detailed verification Plan including test strategy, TB architecture, methodologies to be followed, corner case scenarios, test coverage requirements etc (2.) Mentoring and guiding the team in solving tech. issues (3.) Allocating and tracking tasks (per schedule), CR or risk tracking, support PM in effective project management, coordination of weekly and other team meetings (4.) Conduct test scenarios' identification sessions and come up with a complete set of test plans and critical review of verification artifacts (5.) To prepare test plans for the module or interface owned by self and Coding of test cases as per test plans documented and functional simulation, debugging and fixing