Responsible for all areas of DFT (Design for Test) including architecture and methodologies applicable to unit and chip level, involving all aspects of DFT design functions from scan, MBIST (Memory Built In Self Test), and ATPG (Automatic Test Pattern Generation) insertion and verification, as well as DFD (Design For Debug) features. Responsible for working on both CPU (Central Processing Unit) and SoC (System on Chip) areas of the design and developing test plans both for pre-Silicon (prior to manufacturing) and post-Silicon debugging of the physical product after manufacturing. Responsible for working with logic designers, verification engineers, as well as the physical design and manufacturing test teams. Education: * Master's or foreign equivalent in Electrical Engineering, Electronics Engineering, or related field Experience: * 3 years of experience in job offered or related occupation. Special Requirements: Must have at least 1 year of prior work experience in each of the following: * ATPG (Automatic Test Pattern Generation), 1st Silicon bring-up and test program development. * DFT (Design for Test Methodologies)/MBIST (Memory Built in Self-Test). * Device Physics, Pre-Post Silicon Debug, Characterization. * Failure Analysis Techniques. * Automatic Scripting Statistical Data Analysis. * *Telecommuting allowed for this position* * Position requires significant travel within the United States of America, and fully reimbursed by employer $183,000 - $205,000 a year Worksite:4145 SW Watson Ave, Suite 485, Beaverton, OR 97005 Applicant Instructions:Email resume to:jen@rivosinc.com. Include job code 91914 in reply. EOE.