We use the latest silicon technologies and processes to help our clients create well-designed solutions to highly complex challenges. We are designing and developing next-generation, high performance SoCs, supporting our clients in their drive to deliver their product vision to their users. We are involved in all aspects of chip design from definition and architecture through to verification and signoff. Accenture engineers are true "Silicon to SW" Partners, allowing a new breed of companies in the semiconductor ecosystem to innovate in an unparalleled time to market. You Are: An experienced ... Job Description We Are: The Silicon Design group is a diverse team of world class silicon engineers. We have 100+ years of cumulative hands-on experience in architecture, logic design, verification, physical design, emulation and firmware. We use the latest silicon technologies and processes to help our clients create well-designed solutions to highly complex challenges. We are designing and developing next-generation, high performance SoCs, supporting our clients in their drive to deliver their product vision to their users. We are involved in all aspects of chip design from definition and architecture through to verification and signoff. Accenture engineers are true "Silicon to SW" Partners, allowing a new breed of companies in the semiconductor ecosystem to innovate in an unparalleled time to market. You Are: An experienced SoC Integration Engineer The Work: The ideal candidate can help along the design flow to establish synthesis runs with the related timing constraints, perform Lint, CDC, DFT checks, support regression and release process and analyze STA timing results. Qualification Here's what you need: * A minimum of 2 years of experience with STA (Static Timing Analysis) and PrimeTime and related timing constraints methodology and SDC constraints language * A minimum of 2 years of experience RTL Integration, 3rd Party IP RTL through Lint, CDC check, DFT check with spyglass or VC static and generate clean reports * Bachelor's Degree or equivalent (12 years) work experience (If an, Associate's Degree with 6 years of work experience) Bonus points if: * Proficient with System Verilog/Verilog RTL source code * Proficient with Synopsys Design Compiler and/or Design Compiler Ultra * Python, tcl and other typical scripting languages * Debug flow and tool errors * Familiar with vaml * Familiar with setting up and debugging GLS runs * Familiar with bug tracking systems like Jira * Familiar with revision control systems like Git Compensation at Accenture varies depending on a wide array of factors, which may include but are not limited to the specific office location, role, skill set, and level of experience. As required by local law, Accenture provides a reasonable range of compensation for roles that may be hired in California, Colorado, District of Columbia, Maryland, New York or Washington as set forth below. We accept applications on an on-going basis and there is no fixed deadline to apply. Information on benefits is here. Role Location Annual Salary Range California $63,200 to $188,600 Colorado $63,200 to $163,000 District of Columbia $67,300 to $173,500 New York $58,500 to $188,600 Maryland $58,500 to $150,900 Washington $67,300 to $173,500 #LI-NA Locations